IS42S16100E IS45S16100E
512K Words x 16 Bits x 2 Banks 16Mb SYNCHRONOUS DYNAMIC RAM
FEATURES
* Clock frequency: 200, 166, 143 MHz * Fullysynchronous;allsignalsreferencedtoa positive clock edge * Twobankscanbeoperatedsimultaneouslyand independently * DualinternalbankcontrolledbyA11(bankselect) * Single3.3Vpowersupply * LVTTLinterface * Programmableburstlength -(1,2,4,8,fullpage) * Programmableburstsequence: Sequential/Interleave * 2048refreshcyclesevery32ms(Com,Ind,A1 grade)or16ms(A2grade) * Randomcolumnaddresseveryclockcycle * ProgrammableCASlatency(2,3clocks) * Burstread/writeandburstread/singlewrite operations capability * Burstterminationbyburststopand precharge command * BytecontrolledbyLDQMandUDQM * Packages:400-mil50-pinTSOP-IIand60-ball TF-BGA * TemperatureGrades: Commercial(0oC to +70oC) Industrial(-40oCto+85oC) AutomotiveA1(-40oCto+85oC) AutomotiveA2(-40oCto+105oC) SEPTEMBER 2009
DESCRIPTION ISSI's16MbSynchronousDRAMIS42/4516100Eis
organizedasa524,288-wordx16-bitx2-bankfor improvedperformance.ThesynchronousDRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
PIN CONFIGURATIONS
50-Pin TSOP (Type II)
VDD DQ0 DQ1 GNDQ DQ2 DQ3 VDDQ DQ4 DQ5 GNDQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS A11 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
GND DQ15 DQ14 GNDQ DQ13 DQ12 VDDQ DQ11 DQ10 GNDQ DQ9 DQ8 VDDQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 GND
PIN DESCRIPTIONS
A0-A10 A11 A0-A7 DQ0toDQ15 CLK CKE CS RAS RowAddressInput BankSelectAddress Column Address Input DataDQ SystemClockInput ClockEnable Chip Select RowAddress Strobe Command CAS WE LDQM VDD GND VDDQ NC Column Address Strobe Command WriteEnable LowerBye,Input/OutputMask Power Ground PowerSupplyforDQPin NoConnection
UDQM UpperBye,Input/OutputMask
GNDQ GroundforDQPin
Copyright (c) 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
1
IS42S16100E, IS45S16100E
PIN CONFIGURATION package code: B 60 BaLL Tf-Bga (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball pitch)
1234567 A B C D E F G H J K L M N P R
PIN DESCRIPTIONS
a0-a10 a0-a7 a11 dQ0 to dQ15 cLk cke CS RAS CAS Row address Input column address Input Bank Select address data I/o System clock Input clock enable chip Select Row address Strobe command column address Strobe command WE LdQM, UdQM Vdd gNd Vddq gNdq Nc Write enable x16 Input/output Mask power ground power Supply for I/o pin ground for I/o pin No connection
GND DQ15 DQ14 GND DQ13 VDDQ DQ12 DQ11 DQ10 GNDQ DQ9 VDDQ DQ8 NC NC NC
DQ0
VDD
VDDQ DQ1 GNDQ DQ2 DQ4 DQ3
VDDQ DQ5 GNDQ DQ6 NC VDD LDQM RAS NC NC A0 A2 A3 DQ7 NC WE CAS CS NC A10 A1 VDD
NC UDQM NC CKE A11 A8 A6 GND CLK NC A9 A7 A5 A4
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
PIN FUNCTIONS
TSOP Pin No. Symbol 20to24 27 to 32 A0-A10 Type InputPin Function (In Detail) A0 to A10 are address inputs. A0-A10 are used as row address inputs during active command input and A0-A7 as column address inputs during read or write command input. A10 is also used to determine the precharge mode during other commands. If A10 is LOWduringprechargecommand,thebankselectedbyA11isprecharged,butifA10is HIGH,bothbankswillbeprecharged. WhenA10isHIGHinreadorwritecommandcycle,theprechargestartsautomatically after the burst access. ThesesignalsbecomepartoftheOPCODEduringmoderegistersetcommandinput. A11isthebankselectionsignal.WhenA11isLOW,bank0isselectedandwhenhigh, bank1isselected.ThissignalbecomespartoftheOPCODEduringmoderegisterset command input. CAS, in conjunction with the RAS and WE, forms the device command. See the "CommandTruthTable"itemfordetailsondevicecommands. TheCKEinputdetermineswhethertheCLKinputisenabledwithinthedevice.Whenis CKEHIGH,thenextrisingedgeoftheCLKsignalwillbevalid,andwhenLOW,invalid. WhenCKEisLOW,thedevicewillbeineitherthepower-downmode,theclocksuspend mode,ortheselfrefreshmode.TheCKEisanasynchronousinput. CLKisthemasterclockinputforthisdevice.ExceptforCKE,allinputstothisdeviceare acquired in synchronization with the rising edge of this pin. TheCS input determines whether command input is enabled within the device. Command input is enabled when CSisLOW,anddisabledwithCSisHIGH.Thedevice remains in the previous state when CSisHIGH. DQ0toDQ15areDQpins.DQthroughthesepinscanbecontrolledinbyteunits usingtheLDQMandUDQMpins. LDQMandUDQMcontrolthelowerandupperbytesoftheDQbuffers.Inread mode,LDQMandUDQMcontroltheoutputbuffer.WhenLDQMorUDQMisLOW,the correspondingbufferbyteisenabled,andwhenHIGH,disabled.Theoutputsgo to theHIGHimpedancestatewhenLDQM/UDQMisHIGH.ThisfunctioncorrespondstoOE inconventionalDRAMs.Inwritemode,LDQMandUDQMcontroltheinputbuffer.When LDQMorUDQMisLOW,thecorrespondingbufferbyteisenabled,anddatacanbe writtentothedevice.WhenLDQMorUDQMisHIGH,inputdataismaskedandcannotbe written to the device. RAS, in conjunction with CAS and WE, forms the device command. See the "Command TruthTable"itemfordetailsondevicecommands. WE, in conjunction with RAS and CAS, forms the device command. See the "Command TruthTable"itemfordetailsondevicecommands. VDDQistheoutputbufferpowersupply. VDD is the device internal power supply. GNDQistheoutputbufferground. GND is the device internal ground.
19
A11
InputPin
16 34
CAS CKE
InputPin InputPin
35 18
CLK CS
InputPin InputPin
2,3,5,6,8,9,11 DQ0to 12,39,40,42,43, DQ15 45,46,48,49 14,36 LDQM, UDQM
DQPin InputPin
17 15 7,13,38,44 1,25 4,10,41,47 26,50
RAS WE VDDQ VDD GNDQ GND
InputPin InputPin PowerSupplyPin PowerSupplyPin PowerSupplyPin PowerSupplyPin
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
3
IS42S16100E, IS45S16100E
FUNCTIONAL BLOCK DIAGRAM
CLK CKE CS RAS CAS WE A11
COMMAND DECODER & CLOCK GENERATOR
ROWDECODER
MODE REGISTER
11
11
ROW ADDRESS BUFFER
2048
MEMORYCELL ARRAY
11
BANK 0
DQM
SENSEAMPI/OGATE
A10
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
REFRESH CONTROLLER
SELF REFRESH CONTROLLER
COLUMN ADDRESSBUFFER
BURSTCOUNTER
COLUMN ADDRESSLATCH
DATAIN BUFFER
16 16
256
COLUMNDECODER
8
DQ0-15
8
256
SENSEAMPI/OGATE
REFRESH COUNTER
ROWDECODER
16
DATAOUT BUFFER
16
MULTIPLEXER
11
ROW ADDRESS LATCH
11
ROW ADDRESS BUFFER
2048
MEMORYCELL ARRAY
VDD/VDDQ GND/GNDQ
BANK 1
11
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD max VDDq ViN Vout PD max Ics Topr
max
Parameters MaximumSupplyVoltage MaximumSupplyVoltageforOutputBuffer InputVoltage OutputVoltage AllowablePowerDissipation outputShortedCurrent operatingTemperature StorageTemperature Commerical Industrial A1 A2
Rating
Unit
-1.0to+4.6 V -1.0to+4.6 V -1.0to+4.6 V -1.0to+4.6 V 1 50 0to+70 -40to+85 -40to+85 -40to+105 W mA C C C C
Tstg
-55to+150 C
DC RECOMMENDED OPERATING CONDITION(2) (AtTa = 0oC to +70oCforCommercialtemperature,Ta = -40oCto+85oCforIndustrialandA1temperature,Ta = -40oC to
+105oC for A2 temperature) Symbol VDD, VDDq Vih Vil Parameter SupplyVoltage InputHighVoltage(3) InputLowVoltage(4) Min. 3.0 2.0 -0.3 Typ. 3.3 -- -- Max. 3.6 VDD +0.3 +0.8 Unit V V V
CAPACITANCE CHARACTERISTICS(1,2) (AtTa=0to+25C,VDD=VDDQ=3.30.3V,f=1MHz)
Symbol CiN1 CiN2 CI/O Parameter InputCapacitance:A0-A11 InputCapacitance:(CLK,CKE, CS, RAS, CAS, WE,LDQM,UDQM) DataInput/OutputCapacitance:DQ0-DQ15 Typ. -- -- -- Max. 4 4 5 Unit pF pF pF
Notes: 1.StressgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycausepermanentdamagetothedevice.Thisisa stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sectionsofthisspecificationisnotimplied.Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectreliability. 2.AllvoltagesarereferencedtoGND. 3.Vih(max)=VDDq+1.2Vwithapulsewidth 3 ns. 4.Vil(min)=VDDq-1.2Vwithapulsewidth 3 ns.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
5
IS42S16100E, IS45S16100E
DC ELECTRICAL CHARACTERISTICS (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol iil iol Voh Vol icc1 Parameter InputLeakageCurrent OutputLeakageCurrent OutputHighVoltageLevel OutputLowVoltageLevel OperatingCurrent(1,2) Test Condition Speed 0VViN VDD, with pins other than thetestedpinat0V Outputisdisabled,0V Vout VDD iout=-2mA iout=+2mA OneBankOperation, CASlatency=3 Com. -5 BurstLength=1 Com. -6 trc trc(min.) Com. -7 Iout = 0mA Ind, A1 -6 A2 -6 Ind, A1 -7 A2 -7 Com Ind, A1 tck = Com Ind, A1 A2 tck = tck(miN) tck = Com Ind, A1 A2 CASlatency=3 Com Com Ind, A1 A2 Com Ind,A1 A2 CAS latency = 2 Com Com Ind, A1 A2 Com Ind,A1 A2 tck = tck(miN) -- -- -- -- -- -- -- -- -- -5 -6 -6 -6 -7 -7 -7 -5 -6 -6 -6 -7 -7 -7 Min. -5 -5 2.4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5 5 -- 0.4 170 160 140 170 180 160 170 3 4 2 -- -- 40 30 30 30 170 150 170 180 130 150 160 170 150 170 180 130 150 160 Unit A A V V mA
icc2p Icc2ps
PrechargeStandbyCurrentCKE Vil(max) (InPower-DownMode)
mA
icc3N Icc3Ns
ActiveStandbyCurrent CKE Vih(miN) (InNonPower-DownMode)
mA
icc4
OperatingCurrent (InBurstMode)(1)
tck = tck(miN) Iout =0mA
mA
mA
Notes: 1.Thesearethevaluesattheminimumcycletime.Sincethecurrentsaretransient,thesevaluesdecreaseasthecycletimeincreases.Alsonotethatabypasscapacitorofatleast0.01FshouldbeinsertedbetweenVDD andGNDforeachmemorychip tosuppresspowersupplyvoltagenoise(voltagedrops)duetothesetransientcurrents. 2. Icc1 and Icc4dependontheoutputload.ThemaximumvaluesforIcc1 and Icc4 are obtained with the output open state.
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
DC ELECTRICAL CHARACTERISTICS (RecommendedOperationConditionsunlessotherwisenoted.)
Symbol Parameter icc5 Auto-RefreshCurrent Test Condition trc = trc (miN) CAS latency = 3 Com. Com. Ind, A1 A2 Com Ind, A1 A2 CASlatency=2 Com Com Ind, A1 A2 Com Ind, A1 A2 Speed -5 -6 -6 -6 -7 -7 -7 -5 -6 -6 -6 -7 -7 -7 -- Min. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 120 100 110 120 80 90 100 120 100 110 120 80 90 100 2 Unit mA
mA
icc6
Self-RefreshCurrent
CKE0.2V
mA
Notes: 1.Thesearethevaluesattheminimumcycletime.Sincethecurrentsaretransient,thesevaluesdecreaseasthecycletimeincreases.Alsonotethatabypasscapacitorofatleast0.01FshouldbeinsertedbetweenVDD andGNDforeachmemorychip tosuppresspowersupplyvoltagenoise(voltagedrops)duetothesetransientcurrents. 2. Icc1 and Icc4dependontheoutputload.ThemaximumvaluesforIcc1 and Icc4 are obtained with the output open state.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
7
IS42S16100E, IS45S16100E
AC CHARACTERISTICS(1,2,3)
Symbol Parameter tck3 tck2 tac3 tac2 tchi tcl toh3 toh2 tlz thz3 thz2 tDs tDh tas tah tcks tckh tcka tcs tch trc tras trp trcD trrD tDpl3 tDpl2 tDal3 tDal2 txsr tt tref tref ClockCycleTime AccessTimeFromCLK(4) CLKHIGHLevelWidth CLKLOWLevelWidth OutputDataHoldTime OutputLOWImpedanceTime OutputHIGHImpedanceTime(5) InputDataSetupTime InputDataHoldTime AddressSetupTime AddressHoldTime CKESetupTime CKEHoldTime CKEtoCLKRecoveryDelayTime CommandSetupTime(CS, RAS, CAS, WE,DQM) CommandHoldTime(CS, RAS, CAS, WE,DQM) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) ActiveCommandToRead/WriteCommandDelayTime CommandPeriod(ACT[0]toACT[1]) InputDataToPrecharge CommandDelaytime CASLatency=3 CASLatency=2 CASLatency=3 CASLatency=2 CASLatency=3 CAS Latency=2 CASLatency=3 CASLatency=2 CASLatency=3 CAS Latency=2 -5 Min. Max. 5 -- 8 -- -- -- 5 6 -6 Min. 6 8 Max. -- -- Min. 7 8 -7 Max. -- -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms
-- 5.5 -- 6 2.5 -- 2.5 -- 2.0 -- 2.5 -- 0 -- -- 5.5 -- 6 2 1 2 1 2 1 2 1 -- -- -- -- -- -- -- --
-- 5.5 -- 6 2.5 -- 2.5 -- 2.0 -- 2.5 -- 0 -- -- 5.5 -- 6 2 1 2 1 2 1 2 1 -- -- -- -- -- -- -- --
2 -- 2 -- 2 -- 2.5 -- 0 -- -- -- 5 6
2 -- 1 -- 2 -- 1 -- 2 -- 1 -- 1CLK+3 -- 2 -- 1 -- 50 -- 35 100,000 15 -- 15 -- 10 -- 2CLK -- 2CLK -- 2CLK+trp -- 2CLK+trp -- 55 -- 0.3 1.2 -- 32 -- --
1CLK+3 --
1CLK+3 --
54 -- 36 100,000 18 -- 18 -- 12 -- 2CLK -- 2CLK -- 2CLK+trp -- 2CLK+trp -- 60 -- 0.3 1.2 -- -- 32 --
63 -- 42 100,000 21 -- 21 -- 14 -- 2CLK -- 2CLK -- 2CLK+trp -- 2CLK+trp -- 70 -- 0.3 1.2 -- -- 32 16
InputDataToActive/Refresh CASLatency=3 CommandDelaytime(DuringAuto-Precharge) CAS Latency=2 ExitSelf-RefreshtoActiveTime TransitionTime RefreshCycleTime(2048)fortemperatureTa 85 C
o o
6
RefreshCycleTime(2048)fortemperatureTa >85 C(A2only)
Notes: 1.Whenpowerisfirstapplied,memoryoperationshouldbestarted100safterVDD andVDDq reach their stipulated voltages. Also note that the power-on sequencemustbeexecutedbeforestartingmemoryoperation. 2. measured with tt = 1 ns. 3.Thereferencelevelis1.4Vwhenmeasuringinputsignaltiming.RiseandfalltimesaremeasuredbetweenVih (min.)andVil (max.). 4.Accesstimeismeasuredat1.4Vwiththeloadshowninthefigurebelow. 5.Thetimethz (max.)isdefinedasthetimerequiredfortheoutputvoltagetotransitionby200mVfromVoh (min.)orVol(max.)whenthe output is in the high impedance state. 6.Self-RefreshModeisnotsupportedforA2gradewithTa>85oC.
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
OPERATING FREQUENCY / LATENCY RELATIONSHIPS (CAS Latency=3)
SYMBOL -- -- tcac trcD trac trc tras trp trrD tccD tDpl tDal trbD twbD trql twDl tpql tqmD tDmD tmcD PARAMETER ClockCycleTime OperatingFrequency CASLatency ActiveCommandToRead/WriteCommandDelayTime RASLatency(trcD + tcac) CommandPeriod(REFtoREF/ACTtoACT) CommandPeriod(ACTtoPRE) CommandPeriod(PREtoACT) CommandPeriod(ACT[0]toACT[1]) ColumnCommandDelayTime (READ,READA,WRIT,WRITA) InputDataToPrechargeCommandDelayTime InputDataToActive/RefreshCommandDelayTime (DuringAuto-Precharge) BurstStopCommandToOutputinHIGH-ZDelayTime (Read) BurstStopCommandToInputinInvalidDelayTime (Write) PrechargeCommandToOutputinHIGH-ZDelayTime (Read) PrechargeCommandToInputinInvalidDelayTime (Write) LastOutputToAuto-PrechargeStartTime(Read) DQMToOutputDelayTime(Read) DQMToInputDelayTime(Write) ModeRegisterSetToCommandDelayTime -5 5 200 3 3 6 10 7 3 2 1 2 5 3 0 3 0 -2 2 0 2 -6 6 166 3 3 6 9 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 -7 7 143 3 3 6 9 6 3 2 1 2 5 3 0 3 0 -2 2 0 2 UNITS ns MHz cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle
AC TEST CONDITIONS (Input/OutputReferenceLevel:1.4V) Output Load Input
tCHI
2.8V
tCK
tCL
CLK
1.4V 0.0V 2.8V
50 I/O +1.4V 50pF
tCS
tCH
INPUT 1.4V
0.0V
tOH
tAC
1.4V 1.4V
OUTPUT
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
9
IS42S16100E, IS45S16100E
COMMANDS Active Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
ROW
Read Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
NOPRECHARGE BANK1 COLUMN (1) AUTOPRECHARGE
ROW BANK1
A11
BANK0
A11
BANK0
Write Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10
NOPRECHARGE BANK1 COLUMN(1) AUTOPRECHARGE
Precharge Command
CLK CKE HIGH CS RAS CAS WE A0-A9
BANK0ANDBANK1
A10
BANK0ORBANK1 BANK1
A11
BANK0
A11
BANK0
Don'tCare
Notes: 1.A8-A9=Don'tCare.
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
COMMANDS (cont.) No-Operation Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
HIGH
Device Deselect Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
HIGH
Mode Register Set Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11
OP-CODE
Auto-Refresh Command
CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11
OP-CODE
OP-CODE
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
11
IS42S16100E, IS45S16100E
COMMANDS (cont.) Self-Refresh Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
Power Down Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
ALLBANKSIDLE
NOP NOP
NOP
NOP
Clock Suspend Command
CLK CKE CS RAS CAS WE A0-A9 A10 A11
BANK(S)ACTIVE
Burst Stop Command
CLK CKE
HIGH
NOP NOP
CS RAS CAS WE A0-A9 A10 A11
NOP
NOP
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Mode Register Set Command
(CS, RAS, CAS, WE=LOW) The IS42/4516100E product incorporates a register thatdefinesthedeviceoperatingmode.Thiscommand functions as a data input pin that loads this register from the pins A0 to A11. When power is first applied, the stipulatedpower-onsequenceshouldbeexecutedand thentheIS42/4516100Eshouldbeinitializedbyexecuting a mode register set command. Note that the mode register set command can be executedonlywhenbothbanksareintheidlestate(i.e. deactivated). Another command cannot be executed after a mode register set command until after the passage of the period tmcD, which is the period required for mode register set commandexecution. WhentheA10pinisHIGH,thiscommandfunctionsasa read with auto-precharge command. After the burst read completes, the bank selected by pin A11 is precharged. WhentheA10pinisLOW,thebankselectedbytheA11 pin remains in the activated state after the burst read completes.
Write Command
(CS, CAS, WE=LOW,RAS=HIGH) When burst write mode has been selected with the mode register set command, this command selects the bank specified by the A11 pin and starts a burst write operation atthestartaddressspecifiedbypinsA0toA9.Thisfirst datamustbeinputtotheDQpinsinthecycleinwhich this command. The selected bank must be activated before executing this command. When A10 pin is HIGH, this command functions as a write with auto-precharge command. After the burst write completes, the bank selected by pin A11 is precharged. When the A10 pin is low, the bank selected by the A11 pin remains in the activated state after the burst write completes. After the input of the last burst write data, the application mustwaitforthewriterecoveryperiod(tDpl, tDal)toelapse according to CAS latency.
Active Command
(CS, RAS=LOW,CAS, WE=HIGH) TheIS42/4516100Eincludestwobanksof2048rowseach. Thiscommandselectsoneofthetwobanksaccording to the A11 pin and activates the row selected by the pins A0 to A10. ThiscommandcorrespondstothefalloftheRAS signal fromHIGHtoLOWinconventionalDRAMs.
Precharge Command
(CS, RAS, WE=LOW,CAS=HIGH) Thiscommandstartsprechargingthebankselectedby pinsA10andA11.WhenA10isHIGH,bothbanksare precharged at the same time. When A10 is LOW, the bankselectedbyA11isprecharged.Afterexecutingthis command,thenextcommandfortheselectedbank(s) isexecutedafterpassageoftheperiodtrp, which is the period required for bank precharging. ThiscommandcorrespondstotheRASsignalfromLOW toHIGHinconventionalDRAMs
Auto-Refresh Command
(CS, RAS, CAS=LOW,WE,CKE=HIGH) Thiscommandexecutestheauto-refreshoperation.The row address and bank to be refreshed are automatically generated during this operation. Bothbanksmustbeplacedintheidlestatebeforeexecuting this command. Thestipulatedperiod(trc)isrequiredforasinglerefresh operation,andnoothercommandscanbeexecutedduring this period. Thedevicegoestotheidlestateaftertheinternalrefresh operation completes. Thiscommandmustbeexecutedperiodicallyaccording to trefspecification(ACCharacteristics). This command corresponds to CBR auto-refresh in conventionalDRAMs.
Read Command
(CS, CAS=LOW,RAS, WE=HIGH) ThiscommandselectsthebankspecifiedbytheA11pin and starts a burst read operation at the start address specifiedbypinsA0toA9.DataisoutputfollowingCAS latency. Theselectedbankmustbeactivatedbeforeexecuting this command. Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
13
IS42S16100E, IS45S16100E
Self-Refresh Command
(CS, RAS, CAS,CKE=LOW,WE=HIGH) Thiscommandexecutestheself-refreshoperation.The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation.Theself-refreshoperationisstartedbydropping theCKEpinfromHIGHtoLOW.Theself-refreshoperation continuesaslongastheCKEpinremainsLOWandthere is no need for external control of any other pins. The self-refreshoperationisterminatedbyraisingtheCKE pin from LOW to HIGH.The next command cannot be executeduntilthedeviceinternalrecoveryperiod(txsr) has elapsed. After the self-refresh, since it is impossible to determine the address of the last row to be refreshed, an auto-refresh should immediately be performed for all addresses(4096cycles). Bothbanksmustbeplacedintheidlestatebeforeexecuting this command.
Power-Down Command
(CKE=LOW) Whenbothbanksareintheidle(inactive)state,orwhen atleastoneofthebanksisnotintheidle(inactive)state, this command can be used to suppress device power dissipation by reducing device internal operations to theabsoluteminimum.Power-downmodeisstartedby droppingtheCKEpinfromHIGHtoLOW.Power-down modecontinuesaslongastheCKEpinisheldlow.Allpins otherthantheCKEpinareinvalidandnoneoftheother commandscanbeexecutedinthismode.Thepower-down operationisterminatedbyraisingtheCKEpinfromLOW toHIGH.Thenextcommandcannotbeexecuteduntilthe recoveryperiod(tcka)haselapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation mustbeperformedwithintherefreshperiod(tref).Thus themaximumtimethatpower-downmodecanbeheldis just under the refresh cycle time.
Burst Stop Command
(CS, WE,=LOW,RAS, CAS=HIGH) The command forcibly terminates burst read and write operations.Whenthiscommandisexecutedduringaburst read operation, data output stops after the CAS latency period has elapsed.
Clock Suspend
(CKE=LOW) Thiscommandcanbeusedtostopthedeviceinternal clock temporarily during a read or write cycle. Clock suspendmodeisstartedbydroppingtheCKEpinfrom HIGHtoLOW.Clocksuspendmodecontinuesaslongas theCKEpinisheldLOW.AllinputpinsotherthantheCKE pin are invalid and none of the other commands can be executedinthismode.Alsonotethatthedeviceinternal state is maintained. Clock suspend mode is terminated byraisingtheCKEpinfromLOWtoHIGH,atwhichpoint deviceoperationrestarts.Thenextcommandcannotbe executeduntiltherecoveryperiod(tcka)haselapsed. Since this command differs from the self-refresh command described above in that the refresh operation is not performed automatically internally, the refresh operation mustbeperformedwithintherefreshperiod(tref).Thus themaximumtimethatclocksuspendmodecanbeheld is just under the refresh cycle time.
No Operation
(CS,=LOW,RAS, CAS, WE=HIGH) Thiscommandhasnoeffectonthedevice.
Device Deselect Command
(CS=HIGH) Thiscommanddoesnotselectthedeviceforanobjectof operation. In other words, it performs no operation with respect to the device.
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
COMMAND TRUTH TABLE(1,2)
Symbol Command MRS ModeRegisterSet(3,4) REF Auto-Refresh(5) SREF Self-Refresh(5,6) PRE PrechargeSelectedBank PALL PrechargeBothBanks ACT BankActivate(7) WRIT Write WRITA WriteWithAuto-Precharge(8) READ Read(8) READA ReadWithAuto-Precharge(8) BST BurstStop(9) NOP NoOperation DESL DeviceDeselect SBY ClockSuspend/StandbyMode ENB DataWrite/OutputEnable MASK DataMask/OutputDisable CKE n-1 n H X H H H L H X H X H X H X H X H X H X H X H X H X L X H X H X CS RAS CAS WE DQM L L L L X L L L H X L L L H X L L H L X L L H L X L L H H X L H L L X L H L L X L H L H X L H L H X L H H L X L H H H X H X X X X X X X X X X X X X L X X X X H A11 A10 A9-A0 I/On OPCODE X X X X HIGH-Z X X X HIGH-Z BS L X X X H X X BS Row Row X BS L Column(18) X BS H Column(18) X BS L Column(18) X BS HColumn(18) X X X X X X X X X X X X X X X X X X X X Active X X X HIGH-Z
DQM TRUTH TABLE(1,2)
Symbol ENB MASK ENBU ENBL MASKU MASKL Command DataWrite/OutputEnable DataMask/OutputDisable UpperByteDataWrite/OutputEnable LowerByteDataWrite/OutputEnable UpperByteDataMask/OutputDisable LowerByteDataMask/OutputDisable CKE n-1 n H X H X H X H X H X H X DQM UPPER LOWER L L H H L X X L H X X H
CKE TRUTH TABLE(1,2)
Symbol SPND -- -- REF SELF SELFX PDWN -- Command StartClockSuspendMode ClockSuspend TerminateClockSuspendMode Auto-Refresh StartSelf-RefreshMode TerminateSelf-RefreshMode StartPower-DownMode TerminatePower-DownMode Current State Active OtherStates ClockSuspend Idle Idle Self-Refresh Idle Power-Down CKE n-1 n H L L L L H H H H L L H L H H L H L L H CS RAS CAS WE A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X L L L H X X X L L L H X X X L H H H X X X H X X X X X X L H H H X X X H X X X X X X X X X X X X X 15
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
OPERATION COMMAND TABLE(1,2)
Current State Idle RowActive Read Write ReadWith Auto- Precharge 16 Command DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation NoOperationorPower-Down(12) NoOperationorPower-Down(12) NoOperationorPower-Down Illegal Illegal RowActive NoOperation Auto-RefreshorSelf-Refresh(13) ModeRegisterSet NoOperation NoOperation NoOperation ReadStart(17) WriteStart(17) Illegal(10) Precharge(15) Illegal Illegal BurstReadContinues,RowActiveWhenDone BurstReadContinues,RowActiveWhenDone BurstInterrupted,RowActiveAfterInterrupt BurstInterrupted,ReadRestartAfterInterrupt(16) BurstInterruptedWriteStartAfterInterrupt(11,16) Illegal(10) BurstReadInterrupted,PrechargeAfterInterrupt Illegal Illegal BurstWriteContinues,WriteRecoveryWhenDone BurstWriteContinues,WriteRecoveryWhenDone BurstWriteInterrupted,RowActiveAfterInterrupt BurstWriteInterrupted,ReadStartAfterInterrupt(11,16) BurstWriteInterrupted,WriteRestartAfterInterrupt(16) Illegal(10) BurstWriteInterrupted,PrechargeAfterInterrupt Illegal Illegal BurstReadContinues,PrechargeWhenDone BurstReadContinues,PrechargeWhenDone Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE
Rev. D 08/24/09
Integrated Silicon Solution, Inc. -- www.issi.com
IS42S16100E, IS45S16100E
OPERATION COMMAND TABLE(1,2)
Current State Command Write With DESL Auto-Precharge NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS RowPrecharge DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Immediately DESL Following NOP RowActive BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
Write Recovery DESL NOP BST
Operation
BurstWriteContinues,WriteRecoveryAndPrecharge WhenDone BurstWriteContinues,WriteRecoveryAndPrecharge
CS RAS CAS WE A11 A10 A9-A0
H L X H X H X H X X X X X X
Illegal Illegal Illegal Illegal(10) Illegal(10) Illegal Illegal NoOperation,IdleStateAftertrpHasElapsed NoOperation,IdleStateAftertrp HasElapsed NoOperation,IdleStateAftertrpHasElapsed Illegal(10) Illegal(10) Illegal(10) NoOperation,IdleStateAftertrpHasElapsed(10) Illegal Illegal NoOperation,RowActiveAftertrcDHasElapsed NoOperation,RowActiveAftertrcDHasElapsed NoOperation,RowActiveAftertrcDHasElapsed Illegal(10) Illegal(10) Illegal(10,14) Illegal(10) Illegal Illegal
L L L L L L L H L
L
H H H L L L L X H
H
H L L H H L L X H
H
L H L H L H L X H
L
X X X (18) V V V V V V(18) V V V(18) V V X X X X OPCODE X X X X X X
X X X
L L L L L L H L L L L L L L
H H L L L L X H H H H L L L
L X H
L L H H L L X H H L L H H L
L X H
H L H L H L X H L H L H L H
L X H
V V V(18) V V V(18) V V V(18) V V X X X X OPCODE X X X X X X X X X V V V(18) V V V(18) V V V(18) V X V X X X
L NoOperation,RowActiveAftertDpl HasElapsed H NoOperation,RowActiveAftertDpl HasElapsed L NoOperation,RowActiveAftertDplHasElapsed L
OPCODE X X X X X X
READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS
ReadStart WriteRestart Illegal(10) Illegal(10) Illegal Illegal
L L L L L L
H H H L L L L
H L L H H L L
L H L H L H L
X X X V V V(18) V V V(18) V V V(18) V V X X X X OPCODE
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
17
IS42S16100E, IS45S16100E
OPERATION COMMAND TABLE(1,2)
Current State Command WriteRecovery DESL WithAuto- NOP Precharge BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Refresh DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS ModeRegister DESL Set NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Operation NoOperation,IdleStateAftertDalHasElapsed NoOperation,IdleStateAftertDalHasElapsed NoOperation,IdleStateAftertDalHasElapsed Illegal(10) Illegal(10) Illegal(10) Illegal(10) Illegal Illegal NoOperation,IdleStateAftertrp HasElapsed NoOperation,IdleStateAftertrpHasElapsed NoOperation,IdleStateAftertrpHasElapsed Illegal Illegal Illegal Illegal Illegal Illegal NoOperation,IdleStateAftertmcDHasElapsed NoOperation,IdleStateAftertmcDHasElapsed NoOperation,IdleStateAftertmcDHasElapsed Illegal Illegal Illegal Illegal Illegal Illegal CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE H X X X X X X L H H H X X X L H H L X X X L H L H V V V(18) L H L L V V V(18) L L H H V V V(18) L L H L V V X L L L H X X X L L L L OPCODE
Notes: 1.H:HIGHlevelinput,L:LOWlevelinput,X:HIGHorLOWlevelinput,V:Validdatainput 2.AllinputsignalsarelatchedontherisingedgeoftheCLKsignal. 3.Bothbanksmustbeplacedintheinactive(idle)stateinadvance. 4.ThestateoftheA0toA11pinsisloadedintothemoderegisterasanOPcode. 5.Therowaddressisgeneratedautomaticallyinternallyatthistime.TheDQpinandtheaddresspindataisignored. 6.Duringaself-refreshoperation,allpindata(states)otherthanCKEisignored. 7.Theselectedbankmustbeplacedintheinactive(idle)stateinadvance. 8.Theselectedbankmustbeplacedintheactivestateinadvance. 9.Thiscommandisvalidonlywhentheburstlengthsettofullpage. 10.ThisispossibledependingonthestateofthebankselectedbytheA11pin. 11.Timetoswitchinternalbussesisrequired. 12.TheIS42/4516100Ecanbeswitchedtopower-downmodebydroppingtheCKEpinLOWwhenbothbanksintheidle state.InputpinsotherthanCKEareignoredatthistime. 13.TheIS42/4516100Ecanbeswitchedtoself-refreshmodebydroppingtheCKEpinLOWwhenbothbanksintheidlestate. InputpinsotherthanCKEareignoredatthistime. 14.PossibleiftrrD is satisfied. 15.Illegaliftras is not satisfied. 16.Theconditionsforburstinterruptionmustbeobserved.AlsonotethattheIS42/4516100Ewillentertheprechargedstate immediately after the burst operation completes if auto-precharge is selected. 17. Command input becomes possible after the period trcD haselapsed.AlsonotethattheIS42/4516100Ewillenterthe precharged state immediately after the burst operation completes if auto-precharge is selected. 18. A8,A9 = don't care.
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
CKE RELATED COMMAND TRUTH TABLE(1)
Current State Self-Refresh CKE Operation n-1 n Undefined H X Self-RefreshRecovery(2) L H Self-RefreshRecovery(2) L H Illegal(2) L H (2) Illegal L H Self-Refresh L L IdleStateAftertrcHasElapsed H H Idle State After trcHasElapsed H H Illegal H H Illegal H H Power-DownontheNextCycle H L Power-DownontheNextCycle H L Illegal H L Illegal H L (2) ClockSuspendTerminationontheNextCycle L H ClockSuspend L L Undefined H X Power-DownModeTermination,IdleAfter L H ThatTermination(2) Power-DownMode L L NoOperation H H SeetheOperationCommandTable H H BankActiveOrPrecharge H H Auto-Refresh H H ModeRegisterSet H H SeetheOperationCommandTable H L SeetheOperationCommandTable H L SeetheOperationCommandTable H L Self-Refresh(3) H L SeetheOperationCommandTable H L L X Power-DownMode(3) SeetheOperationCommandTable H H ClockSuspendontheNextCycle(4) H L ClockSuspendTerminationontheNextCycle L H ClockSuspendTerminationontheNextCycle L L CS X H L L L X H L L L H L L L X X X X X H L L L L H L L L L X X X X X RAS CAS WE X X X X X X H H X H L X L X X X X X X X X H H X H L X L X X X X X H H X H L X L X X X X X X X X X X X X X X X X H L L L X H L L L X X X X X X X X H L L X X H L L X X X X X X X X X H L X X X H L X X X X X A11 A10 A9-A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X OPCODE X X X X X X X X X X X X OPCODE X X X X X X X X X X X X X X X
Self-RefreshRecovery Power-Down BothBanksIdle OtherStates
Notes: 1.H:HIGHlevelinput,L:LOWlevelinput,X:HIGHorLOWlevelinput 2.TheCLKpinandtheotherinputarereactivatedasynchronouslybythetransitionoftheCKElevelfromLOWtoHIGH. Theminimumsetuptime(tcka)requiredbeforeallcommandsotherthanmodeterminationmustbesatisfied. 3.Bothbanksmustbesettotheinactive(idle)stateinadvancetoswitchtopower-downmodeorself-refreshmode. 4.Theinputmustbecommanddefinedintheoperationcommandtable.
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Rev. D 08/24/09
19
IS42S16100E, IS45S16100E
TWO BANKS OPERATION COMMAND TRUTH TABLE(1,2)
Operation DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF MRS CS RAS CAS WE A11 A10 A9-A0 H X X X X X X L H H H X X X L H H L X X X L L L L L L H H L L L L L L H H L L H L H L H L Previous State Next State BANK 0BANK 1 BANK 0BANK 1 Any Any Any Any Any Any Any Any R/W/A I/A A I/A I I/A I I/A I/A R/W/A I/A A I/A I I/A I I/A R/W/A I/A RP R/W A A RP I/A R/W/A I/A R R/W A A R R/W/A I/A RP I/A A R/W RP A R/W/A I/A R I/A A R/W R A I/A R/W/A I/A WP R/W A A WP I/A R/W/A I/A W R/W A A W R/W/A I/A WP I/A A R/W WP A R/W/A I/A W I/A A R/W W A Any I Any A I Any A Any R/W/A/I I/A I I I/A R/W/A/I I I I/A R/W/A/I I/A I R/W/A/I I/A R/W/A/I I R/W/A/I I/A I I/A I/A R/W/A/I I R/W/A/I I I I I I I I I
H H CA(3) H H CA(3) H L CA(3) H L CA(3) L H CA(3) L H CA(3) L L CA(3) L L CA(3) H H CA(3) H H CA(3) H L CA(3) H L CA(3) L H CA(3) L H CA(3) L L CA(3) L L CA(3) H RA RA L RA RA X H X X H X H L X H L X L L X L L X X X X OPCODE
Notes: 1.H:HIGHlevelinput,L:LOWlevelinput,X:HIGHorLOWlevelinput,RA:RowAddress,CA:ColumnAddress 2.Thedevicestatesymbolsareinterpretedasfollows: I Idle(inactivestate) A RowActiveState R Read W Write RP ReadWithAuto-Precharge WP WriteWithAuto-Precharge Any Any State 3. CA: A8,A9 = don't care.
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
SIMPLIFIED STATE TRANSITION DIAGRAM (OneBankOperation)
SELF REFRESH
SREFentry SREFexit
MODE REGISTER SET
MRS
IDLE
REF
AUTO REFRESH
CKE_ CKE ACT
IDLE POWER DOWN
ACTIVE POWER DOWN
CKE_ CKE
BST
BANK ACTIVE
WRIT READ
BST
WRIT WRITA READ CKE_ CKE WRITA CKE_ CKE WRITA READA READA
READ
WRITE
WRIT
READ
CKE_
CLOCK SUSPEND
READA CKE_
CKE
CLOCK SUSPEND
WRITEWITH AUTO PRECHARGE
PRE PRE PRE
READWITH AUTO PRECHARGE
CKE
POWERAPPLIED
POWERON
PRE
PRECHARGE
Automatic transition following the completion of command execution. Transition due to command input.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
21
IS42S16100E, IS45S16100E
Device Initialization At Power-On
(Power-OnSequence) AsisthecasewithconventionalDRAMs,theIS42/4516100E productmustbeinitializedbyexecutingastipulatedpoweron sequence after power is applied. After power is applied andVDD andVDDQ reach their stipulatedvoltages,setandholdtheCKEandDQMpins HIGHfor100s.Then,executetheprechargecommand to precharge both bank. Next, execute the auto-refresh command twice or more and define the device operation modebyexecutingamoderegistersetcommand. Themoderegistersetcommandcanbealsosetbefore auto-refresh command.
Burst Length
When writing or reading, data can be input or output data continuously. In these operations, an address is input only once and that address is taken as the starting address internally by the device. The device then automatically generates the following address. The burst length field in the mode register stipulates the number of data items inputoroutputinsequence.IntheIS42/4516100Eproduct, a burst length of 1, 2, 4, 8, or full page can be specified. Seethetableonthenextpagefordetailsonsettingthe mode register.
Burst Type
The burst data order during a read or write operation is stipulated by the burst type, which can be set by the moderegistersetcommand.TheIS42/4516100Eproduct supports sequential mode and interleaved mode burst typesettings.Seethetableonthenextpagefordetails onsettingthemoderegister.Seethe"BurstLengthand ColumnAddressSequence"itemfordetailsonDQdata orders in these modes.
Mode Register Settings
Themoderegistersetcommandsetsthemoderegister. Whenthiscommandisexecuted,pinsA0toA9,A10,and A11 function as data input pins for setting the register, and thisdatabecomesthedeviceinternalOPcode.ThisOP code has four fields as listed in the table below. Input Pin A11,A10,A9,A8,A7 A6,A5,A4 A3 A2,A1,A0 Field ModeOptions CASLatency BurstType BurstLength
Write Mode
Burst write or single write mode is selected by the OP code(A11,A10,A9)ofthemoderegister. AburstwriteoperationisenabledbysettingtheOPcode (A11,A10,A9)to(0,0,0).Aburstwritestartsonthesame cycleasawritecommandset.Thewritestartaddressis specified by the column address and bank select address at the write command set cycle. AsinglewriteoperationisenabledbysettingOPcode(A11, A10,A9)to(0,0,1).Inasinglewriteoperation,dataisonly written to the column address and bank select address specified by the write command set cycle without regard to the bust length setting.
Notethatthemoderegistersetcommandcanbeexecuted only when both banks are in the idle (inactive) state. If the Mode Register Set command is executed, the next command(exceptNOPorDeselect)cannotbeexecuted until at least two clock cycles later, in order to avoid violatingtMCD.
CAS Latency
Duringareadoperation,thebetweentheexecutionofthe read command and data output is stipulated as the CAS latency.This period can be set using the mode register set command. The optimal CAS latency is determined by the clock frequency and device speed grade. See the "OperatingFrequency/LatencyRelationships"itemfor details on the relationship between the clock frequency and the CASlatency.Seethetableonthenextpagefor details on setting the mode register.
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
MODE REGISTER
A11 A10 A9 A8 A7 A6 A5 A4 BT A3 A2 BL A1 A0 W RITEMODE LT ODE M
AddressBus(Ax) ModeRegister(Mx)
M2 BurstLength 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
Sequential Interleaved 1 1 2 2 4 4 8 8 Reserved Reserved Reserved Reserved Reserved Reserved FullPage Reserved
BurstType
M3 0 1
Type Sequential Interleaved
M6 LatencyMode 0 0 0 0 1 1 1 1
M5 0 0 1 1 0 0 1 1
M4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved Reserved Reserved Reserved
M11 0 0
M10 0 0
M9 1 0
M8 0 0
M7 0 0
Write Mode BurstRead&SingleWrite BurstRead&BurstWrite
Note:Othervaluesforthesebitsarereserved.
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
23
IS42S16100E, IS45S16100E
BURST LENGTH AND COLUMN ADDRESS SEQUENCE Burst Length
2 4 8 FullPage (256)
Column Address A2 A1 A0
X X X X X X 0 0 0 0 1 1 1 1 n X X 0 0 1 1 0 0 1 1 0 0 1 1 n 0 1 0 1 0 1 0 1 0 1 0 1 0 1 n
Address Sequence Sequential Interleaved
0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn,Cn+1,Cn+2 Cn+3,Cn+4..... ...Cn-1(Cn+255), Cn(Cn+256)..... 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 None
Notes: 1.Theburstlengthinfullpagemodeis256.
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
BANK SELECT AND PRECHARGE ADDRESS ALLOCATION
Row X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 -- -- -- -- -- -- -- -- -- -- 0 1 0 1 RowAddress RowAddress RowAddress RowAddress RowAddress RowAddress RowAddress RowAddress RowAddress RowAddress PrechargeoftheSelectedBank(PrechargeCommand) RowAddress PrechargeofBothBanks(PrechargeCommand) (Active Bank0Selected(PrechargeandActiveCommand) Bank1Selected(PrechargeandActiveCommand) Column Address Column Address Column Address Column Address Column Address ColumnAddress Column Address Column Address Don'tCare Don'tCare Auto-Precharge-Disabled Auto-Precharge-Enables Bank0Selected(ReadandWriteCommands) Bank1Selected(ReadandWriteCommands)
Command) Column
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Rev. D 08/24/09
25
IS42S16100E, IS45S16100E
Burst Read
Thereadcycleisstartedbyexecutingthereadcommand. Theaddressprovidedduringreadcommandexecutionis usedasthestartingaddress.First,thedatacorrespondingto this address is output in synchronization with the clock signal after the CASlatencyperiod.Next,datacorrespondingto an address generated automatically by the device is output in synchronization with the clock signal. TheoutputbuffersgototheLOWimpedancestateCAS latency minus one cycle after the read command, and go totheHIGHimpedancestateautomaticallyafterthelast data is output. However, the case where the burst length isafullpageisanexception.Inthiscasetheoutputbuffers mustbesettothehighimpedancestatebyexecutinga burst stop command. Note that upper byte and lower byte output data can be masked independently under control of the signals appliedtotheU/LDQMpins.Thedelayperiod(tqmD)is fixedattwo,regardlessoftheCAS latency setting, when this function is used. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
CLK COMMAND UDQM LDQM DQ8-DQ15 DQ0-DQ7
READ(CA=A,BANK0)
READA0 tQMD=2
DOUT A0 DOUT A0
HI-Z
DOUT A2
DOUT A3
HI-Z
DOUT A1
HI-Z
DATAMASK(LOWERBYTE)
CAS latency = 3, burst length = 4
DATAMASK(UPPERBYTE)
Burst Write
Thewritecycleisstartedbyexecutingthecommand.The addressprovidedduringwritecommandexecutionisused as the starting address, and at the same time, data for this address is input in synchronization with the clock signal. Next, data is input in other in synchronization with the clock signal. During this operation, data is written to addressgeneratedautomaticallybythedevice.Thiscycle terminates automatically after a number of clock cycles determined by the stipulated burst length. However, the casewheretheburstlengthisafullpageisanexception. Inthiscasethewritecyclemustbeterminatedbyexecuting aburststopcommand.ThelatencyforDQpindatainput
CLK
is zero, regardless of the CAS latency setting. However, a waitperiod(writerecovery:tDpl)afterthelastdatainputis required for the device to complete the write operation. Notethattheupperbyteandlowerbyteinputdatacan be masked independently under control of the signals applied to the U/LDQM pins.The delay period (tDmD) is fixedatzero,regardlessoftheCAS latency setting, when this function is used. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
COMMAND DQ
WRITE DIN 0 DIN 1 DIN 2 DIN 3
BURSTLENGTH
CAS latency = 2,3, burst length = 4 26 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read With Auto-Precharge
Thereadwithauto-prechargecommandfirstexecutesa burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this command performs a read command and a precharge command in a single operation. Duringthisoperation,thedelayperiod(tpql)betweenthe last burst data output and the start of the precharge operation differs depending on the CAS latency setting. When the CAS latency setting is two, the precharge operation starts on one clock cycle before the last burst data is output(tpql=-1).WhentheCAS latency setting is three, the precharge operation starts on two clock cycles beforethelastburstdataisoutput(tpql=-2).Therefore, the selected bank can be made active after a delay of trp from the start position of this precharge operation. Theselectedbankmustbesettotheactivestatebefore executingthiscommand. Theauto-prechargefunctionisinvalidiftheburstlength is set to full page. CAS Latency tpql 3 -2 2 -1
CLK COMMAND DQ
READWITHAUTO-PRECHARGE (BANK0)
READA 0 tPQL DOUT0 DOUT1 DOUT2 DOUT3 tRP
ACT0
PRECHARGESTART
CAS latency = 2, burstlength = 4
CLK COMMAND DQ
READWITHAUTO-PRECHARGE (BANK0)
READA 0 tPQL DOUT0
PRECHARGESTART
ACT0
DOUT1
DOUT2 tRP
DOUT3
CAS latency = 3, burstlength = 4
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Rev. D 08/24/09
27
IS42S16100E, IS45S16100E
Write With Auto-Precharge
Thewritewithauto-prechargecommandfirstexecutesa burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this command performs a write command and a precharge command in a single operation. Duringthisoperation,thedelayperiod(tDal) between the last burst data input and the completion of the precharge operation differs depending on the CAS latency setting. Thedelay(tDal)istrpplustwoCLKperiods.Thatis,the precharge operation starts two clock periods after the last burst data input. Therefore,theselectedbankcanbemadeactiveaftera delay of tDal. Theselectedbankmustbesettotheactivestatebefore executingthiscommand. Theauto-prechargefunctionisinvalidiftheburstlength is set to full page. CAS Latency tDal 3 2CLK +trp 2 2CLK +trp
CLK COMMAND DQ
WRITEA0
PRECHARGESTART
ACT0 DIN1 DIN2 DIN3 tRP tDAL
DIN0
WRITEWITHAUTO-PRECHARGE (BANK0)
CAS latency = 2, burstlength = 4
CLK COMMAND DQ
WRITEA0
PRECHARGESTART
ACT0 DIN1 DIN2 DIN3 tRP tDAL
DIN0
WRITEWITHAUTO-PRECHARGE (BANK0)
CAS latency = 3, burstlength = 4
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Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Interval Between Read Command
Anewcommandcanbeexecutedwhileareadcycleis in progress, i.e., before that cycle completes. When the secondreadcommandisexecuted,aftertheCAS latency has elapsed, data corresponding to the new read command is output in place of the data due to the previous read command. Theintervalbetweentworeadcommand(tccD)mustbe at least one clock cycle. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
CLK COMMAND DQ
tCCD
READ(CA=A,BANK0) READ(CA=B,BANK0)
READA0
READB0 DOUT A0 DOUTB0 DOUTB1 DOUTB3
DOUTB2
CAS latency = 2, burstlength = 4
Interval Between Write Command
Anewcommandcanbeexecutedwhileawritecycleisin progress, i.e., before that cycle completes. At the point the secondwritecommandisexecuted,datacorresponding to the new write command can be input in place of the data for the previous write command. Theintervalbetweentwowritecommands(tccD)mustbe at least one clock cycle. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
CLK
tCCD
COMMAND DQ
WRITEA0 DIN A0
WRITEB0 DINB0 DINB1 DINB2 DINB3
WRITE(CA=A,BANK0) WRITE(CA=B,BANK0)
CAS latency = 3, burstlength = 4
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Rev. D 08/24/09
29
IS42S16100E, IS45S16100E
Interval Between Write and Read Commands
Anewreadcommandcanbeexecutedwhileawritecycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency has elapsed from the point the new read commandwasexecuted.TheI/Onpinsmustbeplacedin theHIGHimpedancestateatleastonecyclebeforedata is output during this operation. The interval (tccD) between command must be at least one clock cycle. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
CLK
tCCD
COMMAND DQ
WRITEA0 DIN A0
READB0 DOUTB0 DOUTB1 DOUTB2 DOUTB3
HI-Z
WRITE(CA=A,BANK0)
READ(CA=B,BANK0)
CAS latency = 2, burstlength = 4
CLK
tCCD
COMMAND DQ
WRITEA0 DIN A0
READB0 DOUTB0 DOUTB1 DOUTB2 DOUTB3
HI-Z
READ(CA=B,BANK0)
WRITE(CA=A,BANK0)
CAS latency = 3, burstlength = 4
30
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Interval Between Read and Write Commands
A read command can be interrupted and a new write commandexecutedwhilethereadcycleisinprogress, i.e.,beforethatcyclecompletes.Datacorresponding to the new write command can be input at the point newwritecommandisexecuted.Topreventcollision betweeninputandoutputdataattheDQnpinsduring this operation, the outputdatamustbemaskedusingtheU/LDQMpins.The interval(tccD)betweenthesecommandsmustbeatleast one clock cycle. Theselectedbankmustbesettotheactivestatebefore executingthiscommand.
CLK
tCCD
COMMAND U/LDQM DQ
READA0
WRITEB0
HI-Z
DINB0
DINB1
DINB2
DINB3
READ(CA=A,BANK0)
WRITE(CA=B,BANK0)
CAS latency = 2, 3, burstlength = 4
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
31
IS42S16100E, IS45S16100E
Precharge
TheprechargecommandsetsthebankselectedbypinA11 totheprechargedstate.Thiscommandcanbeexecutedat a time tras followingtheexecutionofanactivecommand to the same bank. The selected bank goes to the idle state at a time trpfollowingtheexecutionoftheprecharge command,andanactivecommandcanbeexecutedagain for that bank. IfpinA10islowwhenthiscommandisexecuted,thebank selected by pin A11 will be precharged, and if pin A10 is HIGH,bothbankswillbeprechargedatthesametime.This input to pin A11 is ignored in the latter case.
Read Cycle Interruption Using the Precharge Command
Areadcyclecanbeinterruptedbytheexecutionofthe prechargecommandbeforethatcyclecompletes.The delaytime(trql)fromtheexecutionoftheprecharge command to the completion of the burst output is the clock cycle of CAS latency. CAS Latency trql 3 3 2 2
CLK
tRQL
COMMAND DQ
READA0
PRE0
DOUT A0 DOUT A1 DOUT A2
READ(CA=A,BANK0) PRECHARGE(BANK0)
HI-Z
CAS latency = 2, burstlength = 4
CLK
tRQL
COMMAND DQ
READA0
PRE0
DOUT A0 DOUT A1 DOUT A2
READ(CA=A,BANK0) PRECHARGE(BANK0)
HI-Z
CAS latency = 3, burstlength = 4
32
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle Interruption Using the Precharge Command
Awritecyclecanbeinterruptedbytheexecutionofthe precharge command before that cycle completes. The delaytime(twDl)fromtheprechargecommandtothepoint where burst input is invalid, i.e., the point where input data is no longer written to device internal memory is zero clock cycles regardless of the CAS. Toinhibitinvalidwrite,theDQMsignalmustbeasserted HIGHwiththeprechargecommand. Thisprechargecommandandburstwritecommandmust be of the same bank, otherwise it is not precharge interrupt but only another bank precharge of dual bank operation. Inversely, to write all the burst data to the device, the prechargecommandmustbeexecutedafterthewrite datarecoveryperiod(tDpl)haselapsed.Therefore,the prechargecommandmustbeexecutedtwoclockcycles after the input of the last burst data item. CAS Latency twDl tDpl 3 0 2 2 0 2
CLK
tWDL=0
COMMAND DQM DQ
WRITEA0
PRE0
DIN A0
DIN A1
DIN A2
DIN A3
MASKEDBYDQM
WRITE(CA=A,BANK0)
PRECHARGE(BANK0)
CAS latency = 2, burstlength = 4
CLK
tDPL
COMMAND DQ
WRITEA0
PRE0 A1 DIN A2 DIN A3
PRECHARGE(BANK0)
DIN A0 DIN
WRITE(CA=A,BANK0)
CAS latency = 3, burstlength = 4
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33
IS42S16100E, IS45S16100E
Read Cycle (Full Page) Interruption Using the Burst Stop Command
The IS42/4516100E can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full page. The IS42/4516100E repeats the operation starting at the256thcyclewiththedataoutputreturningtolocation (a)andcontinuingwitha+1,a+2,a+3,etc.Aburststop command must be executed to terminate this cycle. A precharge command must be executed within the ACT toPREcommandperiod(trasmax.)followingtheburst stop command. Aftertheperiod(trbD)requiredforburstdataoutputto stopfollowingtheexecutionoftheburststopcommand haselapsed,theoutputsgototheHIGHimpedance state.Thisperiod(trbD)istwoclockcyclewhenthe CAS latency is two and three clock cycle when the CAS latency is three. CAS Latency trbD 3 3 2 2
CLK
tRBD
COMMAND DQ
READA0
BST
DOUT A0 DOUT A0
READ(CA=A,BANK0)
DOUT A1
DOUT A2
BURSTSTOP
DOUT A3
HI-Z
CAS latency = 2, burstlength = 4
CLK
tRBD
COMMAND DQ
READA0
BST
DOUT A0 DOUT A0
READ(CA=A,BANK0)
DOUT A1
BURSTSTOP
DOUT A2
DOUT A3
HI-Z
CAS latency = 3, burstlength = 4
34
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle (Full Page) Interruption Using the Burst Stop Command
TheIS42/4516100Ecaninputdatacontinuouslyfrom theburststartaddress(a)tolocationa+255duringa write cycle in which the burst length is set to full page. TheIS42/4516100Erepeatstheoperationstartingat the256thcyclewithdatainputreturningtolocation(a) and continuing with a+1, a+2, a+3, etc. A burst stop commandmustbeexecutedtoterminatethiscycle.A precharge command mustbeexecutedwithintheACTtoPREcommand period(trasmax.)followingtheburststopcommand. Aftertheperiod(twbD)requiredforburstdatainputto stopfollowingtheexecutionoftheburststopcommand haselapsed,thewritecycleterminates.Thisperiod (twbD)iszeroclockcycles,regardlessoftheCAS latency.
CLK
tWBD=0 tRP
PRE0
COMMAND DQ
WRITEA0
BST
INVALIDDATA
DIN A0
DIN A1
DIN A
DIN A1
DIN A2
BURSTSTOP PRECHARGE(BANK0)
READ(CA=A,BANK0)
Don'tCare
Burst Data Interruption Using the U/LDQM Pins (Read Cycle)
Burstdataoutputcanbetemporarilyinterrupted(masked) duringareadcycleusingtheU/LDQMpins.Regardlessof the CASlatency,twoclockcycles(tqmD)afteroneofthe U/LDQMpinsgoesHIGH,thecorrespondingoutputsgo totheHIGHimpedancestate.Subsequently,theoutputs are maintained in the high impedance state as long as thatU/LDQMpinremainsHIGH.WhentheU/LDQMpin goesLOW,outputisresumedatatimetqmDlater.This output control operates independently on a byte basis with the UDQM pin controlling upper byte output (pins DQ8-DQ15) and the LDQM pin controlling lower byte output(pinsDQ0toDQ7). SincetheU/LDQMpinscontrolthedeviceoutputbuffers only, the read cycle continues internally and, in particular, incrementing of the internal burst counter continues.
CLK COMMAND UDQM LDQM DQ8-DQ15 DQ0-DQ7
READ(CA=A,BANK0)
READA0 tQMD=2
DOUT A0 DOUT A0
HI-Z
DOUT A2
DOUT A3
HI-Z
DOUT A1
HI-Z
DATAMASK(LOWERBYTE)
DATAMASK(UPPERBYTE)
CAS latency = 2, burstlength = 4 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
35
IS42S16100E, IS45S16100E
Burst Data Interruption U/LDQM Pins (Write Cycle)
Burstdatainputcanbetemporarilyinterrupted(muted) duringawritecycleusingtheU/LDQMpins.Regardless of the CASlatency,assoonasoneoftheU/LDQMpins goes HIGH, the corresponding externally applied input data will no longer be written to the device internal circuits. Subsequently, the corresponding input continues to be mutedaslongasthatU/LDQMpinremainsHIGH. TheIS42/4516100Ewillreverttoacceptinginputassoon as
CLK COMMAND UDQM
tDMD=0 WRITEA0
thatpinisdroppedtoLOWanddatawillbewrittentothe device.Thisinputcontroloperatesindependentlyonabyte basiswiththeUDQMpincontrollingupperbyteinput(pin DQ8 to DQ15) and the LDQM pin controlling the lower byteinput(pinsDQ0toDQ7). SincetheU/LDQMpinscontrolthedeviceinputbuffers only, the cycle continues internally and, in particular, incrementing of the internal burst counter continues.
LDQM DQ8-DQ15 DQ0-DQ7
WRITE(CA=A,BANK0)
DIN A1 DIN A0
DATAMASK(LOWERBYTE)
DIN A2
DIN A3 DIN A3
DATAMASK(UPPERBYTE)
Don'tCare
CAS latency = 2, burstlength = 4
Burst Read and Single Write
Theburstreadandsinglewritemodeissetupusingthe moderegistersetcommand.Duringthisoperation,theburst read cycle operates normally, but the write cycle only writes asingledataitemforeachwritecycle.TheCAS latency andDQMlatencyarethesameasinnormalmode.
CLK COMMAND DQ
WRITEA0
DIN A0
WRITE(CA=A,BANK0)
CAS latency = 2, 3 36 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Bank Active Command Interval
When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, thebankcanbeactivatedbyexecutingtheactive command. If the other bank is in the idle state at that time,theactivecommandcanbeexecutedforthatbank after the period trrD has elapsed. At that point both banks will be in the active state. When a bank active commandhasbeenexecuted,aprechargecommand mustbeexecutedforthatbankwithintheACTtoPRE commandperiod(trasmax).Alsonotethataprecharge commandcannotbeexecutedforanactivebankbefore tras(min)haselapsed. After a bank active command has been executed and thetrcdperiodhaselapsed,readwrite(includingautoprecharge)commandscanbeexecutedforthatbank.
CLK
tRRD
COMMAND
ACT0
ACT1
BANKACTIVE(BANK1)
BANKACTIVE(BANK0)
CLK
tRCD
COMMAND
ACT0
READ0
BANKACTIVE(BANK0)
BANKACTIVE(BANK0)
CAS latency = 3
Clock Suspend
WhentheCKEpinisdroppedfromHIGHtoLOWduring a read or write cycle, the IS42/4516100E enters clock suspendmodeonthenextCLKrisingedge.Thiscommand reduces the device power dissipation by stopping the device internal clock. Clock suspend mode continues as longastheCKEpinremainslow.Inthisstate,allinputs otherthanCKEpinareinvalidandnoothercommands can be executed. Also, the device internal states are maintained.WhentheCKEpingoesfromLOWtoHIGH clocksuspendmodeisterminatedonthenextCLKrising edge and device operation resumes. Thenextcommandcannotbeexecuteduntiltherecovery period(tcka)haselapsed. Since this command differs from the self-refresh command described previously in that the refresh operation is not performed automatically internally, the refresh operation mustbeperformedwithintherefreshperiod(tref).Thus themaximumtimethatclocksuspendmodecanbeheld is just under the refresh cycle time.
CLK
CKE COMMAND DQ
READ(BANK0)
READ0 DOUT 0 DOUT 1 DOUT 2 DOUT 3
CLOCKSUSPEND
CAS latency = 2, burstlength = 4 Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
37
IS42S16100E, IS45S16100E
OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle
T0 CLK
tCK
T1
tCHI
T2
T3
T10
T17
T18
T19
T20
tCL
CKE HIGH
tCS
tCH tCS tCH tCH tCH tAS tAH CODE tAS tAH
BANK0&1
CS RAS
tCS
CAS
tCS
WE A0-A9
tAS CODE tAS tAH CODE BANK0 ROW tAH ROW BANK1
A10 A11 DQM HIGH DQ
WAITTIME T=100s
tRP
tRC
tRC
tMCD
tRAS tRC
Undefined
CAS latency = 2, 3
Don'tCare
38
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Power-Down Mode Cycle
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
Tn
Tn+1
tCKH tCKA
Tn+2
Tn+3
tCL
tCKS
CKE
tCS
CS
tCH tCH tCH tAS tAH ROW tAS tAH
BANK0&1 BANK0OR1
RAS
tCS
CAS
tCS
WE A0-A9 A10 A11 DQM DQ
tRP POWERDOWNMODE EXIT POWERDOWNMODE tRAS tRC
ROW BANK1 BANK0
BANK1 BANK0
Undefined
CAS latency = 2, 3
Don'tCare
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Rev. D 08/24/09
39
IS42S16100E, IS45S16100E
Auto-Refresh Cycle
T0 CLK
tCKS tCK tCH tCS tCH tCH tCH tCHI tCL
T1
T2
T3
Tl
Tm
Tn
Tn+1
CKE
tCS
CS RAS
tCS
CAS
tCS
WE A0-A9
tAS tAH
BANK0&1
ROW ROW BANK1
A10 A11
BANK0
DQM DQ
tRP [ tRC ][ tRC ][ tRC tRAS tRC]
Undefined
CAS latency = 2, 3
Don'tCare
40
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Self-Refresh Cycle
T0
T1 tCHI
T2
T3
Tm
Tm+1
Tm+2
Tn
CLK
tCKS tCK tCKA tCS tCH tCS tCH tCH tCH tCL tCKS
CKE CS RAS
tCS
CAS
tCS
WE A0-A9
tAS tAH
BANK0&1
A10 A11 DQM DQ
tRP
SELFREFRESHMODE
tXSR
tRC
Undefined
CAS latency = 2, 3
Note: 1: a8, a9 = don't care. 2. Self-Refresh Mode is not supported for a2 grade with Ta > 85oc.
Don'tCare
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41
IS42S16100E, IS45S16100E
Read Cycle
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tQMD tAC tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm BANK0AND1 NOPRE BANK1 BANK0OR1 BANK1 tCH BANK0 tAC tOH
DOUT m+1
ROW ROW BANK1 BANK0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tRCD tRAS tRC tLZ tCAC
tRQL tRP
tHZ
tRCD tRAS tRC
Undefined
CAS latency = 2, burstlength = 4 Note1:A8,A9=Don'tCare.
Don'tCare
42
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tQMD tAC tAC tOH
DOUT m (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMNm AUTOPRE BANK1 tCH tAC tOH
DOUT m+1
ROW ROW BANK1 BANK0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC tCAC
tPQL tRP
tHZ
tRCD tRAS tRC
Undefined
CAS latency = 2, burstlength = 4 Note1:A8,A9=Don'tCare.
Don'tCare
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Rev. D 08/24/09
43
IS42S16100E, IS45S16100E
Read Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tQMD tAC tAC tOH
DOUT 0m (1)
T1
tCHI
T2
T3
T4
T5
T6
T260
T261
T262
T263
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN
BANK0OR1 BANK0 tCH tAC tOH
DOUT 0m+1
tAC tOH
DOUT 0m-1
tAC tOH
DOUT 0m
tOH
DOUT 0m+1
DQ
tLZ tRCD tRAS
(BANK0) (BANK0)
tCAC
tRBD
tHZ tRP
(BANK0)
tRC
Undefined
CAS latency = 2, burstlength = full page Note1:A8,A9=Don'tCare.
Don'tCare
44
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Ping-Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tQMD tAC tAC tOH tOH
DOUT 0m+1 DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTOPRE
ROW ROW
COLUMN AUTOPRE
ROW ROW
NOPRE BANK1 BANK1
BANK0OR1 BANK0 tCH tAC tAC tOH
DOUT 1m
BANK0OR1 BANK0 BANK1
tOH
DOUT 1m+1
DQ
(BANK0TO1) (BANK0) (BANK0) (BANK0)
tRRD
tLZ tCAC tRCD
tHZ
(BANK1) (BANK1)
tLZ
tHZ
(BANK0) (BANK0) (BANK0)
tRCD
(BANK1)
tCAC
tRCD
tRAS tRC
(BANK0)
tRP
tRAS tRC
(BANK1) (BANK1)
tRAS tRC
(BANK1)
tRP
Undefined
CAS latency = 2, burstlength = 2 Note1:A8,A9=Don'tCare.
Don'tCare
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45
IS42S16100E, IS45S16100E
Write Cycle
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tCH NOPRE BANK1 BANK0OR1 BANK1 BANK0
(1)
RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMNm BANK0AND1
ROW ROW BANK1 BANK0
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDPL tRP tRCD tRAS tRC
DQ
tRCD tRAS tRC
Undefined
CAS latency = 2, burstlength = 4 Note1:A8,A9=Don'tCare.
Don'tCare
46
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tCH BANK0 AUTOPRE BANK1 ROW BANK1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm
ROW
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDAL tRP tRCD tRAS tRC
DQ
tRCD tRAS tRC
Undefined
CAS latency = 2, burstlength = 4 Note1:A8,A9=Don'tCare.
Don'tCare
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Rev. D 08/24/09
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IS42S16100E, IS45S16100E
Write Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tCH BANK0OR1 BANK0 tCHI tCL
T1
T2
T3
T4
T5
T258
T259
T260
T261
T262
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH DIN 0m-1 DIN0m tDPL tRP
DQ
tRCD tRAS tRC
Undefined
CAS latency = 2, burst length = full page Note1:A8,A9=Don'tCare.
Don'tCare
48
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Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Ping-Pong Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 BANK1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTOPRE
ROW ROW
COLUMN AUTOPRE
ROW ROW
NOPRE BANK1
BANK0OR1 BANK0 BANK0 tCH
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH tDS DIN 0m+3 tDPL
tDH tDS DIN 1m
tDH tDS DIN 1m+1
tDH tDS DIN 1m+2
tDH DIN 1m+3 tDPL
DQ
(BANK0TO1) (BANK0) (BANK0) (BANK0)
tRRD
tRCD
(BANK1)
tRCD
tRAS tRC
(BANK0)
tRP
(BANK0) (BANK0) (BANK0)
tRCD
tRAS tRC
(BANK1) (BANK1)
tRAS tRC
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
49
IS42S16100E, IS45S16100E
Read Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 tCS tQMD tAC BANK0 tCH tAC tOH
DOUT n
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1 BANK0OR1 BANK1 BANK0
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tAC tOH
DOUT n+1
tAC tOH
DOUTo
tOH
DOUT o+1
DQ
tLZ tRCD tRAS tRC tCAC
tHZ tCAC tCAC tRQL tRP
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
50
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE NOPRE BANK1 tCS tQMD tAC tCH tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1 BANK0OR1 BANK1 BANK0
BANK0
tQMD tAC
tAC tOH
DOUT m+1
tAC tOH
DOUTo
tOH
DOUT n
tOH
DOUT o+1
DQ
tLZ tRCD tRAS tRC tCAC
tHZ tCAC
tLZ tCAC tRQL tRP
tHZ
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
51
IS42S16100E, IS45S16100E
Write Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 tCS BANK0 tCH BANK0OR1 BANK1 BANK0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DINn
tDH tDS DINn+1
DQ
tRCD tRAS tRC
tDH tDS tDH DINo DINo+1 tDPL tRP
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
52
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 BANK0 NOPRE BANK1 BANK0 BANK1OR0 BANK1 BANK0
(1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1
tCS
tCH
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DINn
tDS
tDH tDS DINo
tDH DINo+1 tDPL tRP
DQ
tRCD tRAS tRC
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
53
IS42S16100E, IS45S16100E
Read Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS NOPRE BANK1 BANK0 BANK0OR1 tCH BANK1 BANK0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK1 BANK0
tQMD
tAC
tAC tOH tOH
DOUT m+1 DOUT m
DQ
tLZ tRCD tRAS tRC tCAC
tHZ tRP tRAS tRC
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
54
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS NOPRE BANK1 BANK0 BANK0OR1 BANK1 BANK0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK1 BANK0
tCH
tDS
tDH DIN m
tDS DIN m+1
tDH
DQ
tRCD tRAS tRC
tDPL tRP tRAS tRC
Undefined
CAS latency = 2, burst length = 2 Note1:A8,A9=Don'tCare.
T0 CLK
tCKS
t
CKE
tCS
tC t
CS RAS
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
tC
55
tC
CAS
IS42S16100E, IS45S16100E
Read Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tQMD tAC tCH tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMNm
ROW ROW BANK0OR1 BANK0 BANK0 BANK1
COLUMNn AUTOPRE NOPRE BANK1 BANK0
tAC tOH
DOUT m+1
tHZ tOH
DOUT m+2
DQ
tLZ tRCD tRAS tRC tCAC
tRQL tRP
tRCD tRAS tRC
tCAC
Undefined
CAS latency = 2, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
56
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tCH BANK0OR1 BANK0 tCS tCH BANK0 ROW BANK1 NOPRE BANK1 BANK0 tCS tDH
DIN 0n
RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMNm
ROW
COLUMNn AUTOPRE
tDS
tDH tDS
DIN 0m DIN 0m+1
tDH tDS
DIN 0m+2
tDH
tDS
DQ
tRCD tRAS tRC
tRCD tRP tRAS tRC
Undefined
CAS latency = 2, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
57
IS42S16100E, IS45S16100E
Read Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 tCH BANK0OR1 BANK1 tQMD tQMD tAC tLZ BANK0 BANK0
(1)
RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 UDQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK1
tCS tCS
tCH tHZ tOH
DOUT m
LDQM
tAC tLZ tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ8-15
tAC tLZ
tAC tOH
DOUT m
tOH
DOUT m+1
DQ0-7
tRCD tRAS tRC tCAC
tQMD
tRQL tRP
tRCD tRAS tRC
Undefined
CAS latency = 2, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
58
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 tCH BANK0OR1 BANK1 BANK0 BANK0 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 UDQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK1
tCS tCS
tCH tDS tDH DIN m DIN m+1 tDH DIN m tDS DIN m+3 tDPL tRP tRCD tRAS tRC tDH tDS DIN m+3 tDH
LDQM
tDS tDH
DQ8-15
tDS
DQ0-7
tRCD tRAS tRC
Undefined
CAS latency = 2, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
59
IS42S16100E, IS45S16100E
Read Cycle, Write Cycle / Burst Read, Single Write
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tQMD tAC tAC tOH
DOUT m (1) (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMNm NOPRE BANK1
COLUMNn AUTOPRE NOPRE BANK1 tCH tAC tOH
DOUT m+1
BANK0AND1 BANK0OR1 BANK1 BANK0
BANK0
tAC tOH
DOUT m+2
tDS tOH
DOUT m+3 DIN n
tDH
DQ
tLZ tRCD tRAS tRC tCAC
tHZ tDPL tRP
Undefined
CAS latency = 2, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
60
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 BANK0 tCS tQMD tAC tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm BANK0AND1 NOPRE BANK1 BANK0OR1 BANK1 tCH BANK0 tAC tOH
DOUT m+1
ROW ROW BANK1 BANK0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC tCAC
tRQL tRP
tHZ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
61
IS42S16100E, IS45S16100E
Read Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 BANK0 tCS tQMD tAC tAC tOH
DOUT m (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
A0-A9 A10 A11 DQM
COLUMN AUTOPRE
ROW ROW
BANK1 tCH tAC tOH
DOUT m+1
BANK1 BANK0
tAC tOH
DOUT m+2
tOH
DOUT m+3
DQ
tLZ tRCD tRAS tRC tCAC
tPQL tRP
tHZ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
T0 CLK
tCKS tCK
CKE
tCS
tCKA tCH tCS
CS RAS CAS
62
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
tCS
IS42S16100E, IS45S16100E
Read Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 BANK0 tCS tCH tAC tAC tOH
DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T262
T263
T264
T265
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN NOPRE BANK0OR1 BANK0
tAC tOH
DOUT 0m+1
tAC tOH
DOUT 0m-1
tAC tOH
DOUT 0m
tOH
DOUT 0m+1
DQ
tLZ
(BANK0) (BANK0) (BANK0)
tRCD
tRAS tRC
(BANK0)
tCAC
tRBD
(BANK0)
tHZ tRP
Undefined
CAS latency = 3, burst length = full page Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
63
IS42S16100E, IS45S16100E
Read Cycle / Ping Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 BANK1 ROW NOPRE BANK0 tCS tQMD tAC tLZ tAC tOH
DOUT 0m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
ROW
COLUMN AUTOPRE
COLUMN AUTOPRE
ROW ROW
NOPRE BANK1
BANK0OR1 BANK0
BANK0OR1 BANK1 tCH tAC tOH
DOUT 0m+1
BANK0
tAC tOH
DOUT 1m
tOH
DOUT 1m+1
DQ
(BANK0TO1) (BANK0) (BANK0) (BANK0)
tRRD
(BANK1) (BANK0)
tRCD
(BANK1)
tCAC
tHZ
(BANK0) (BANK0)
tRCD
tCAC
tRQL tRP
(BANK0) (BANK0) (BANK0)
tRCD tRAS tRC
tRAS tRC
(BANK1) (BANK1)
tRAS tRC
(BANK1)
tRP
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
64
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tCH NOPRE BANK1 BANK0OR1 BANK1 BANK0
RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN BANK0AND1
ROW ROW BANK1 BANK0
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDPL tRP tRCD tRAS tRC
DQ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
65
IS42S16100E, IS45S16100E
Write Cycle / Auto-Precharge
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS BANK0 tCH BANK0 BANK1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMN AUTOPRE
ROW ROW BANK1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH tDS DIN m+2
tDH DIN m+3 tDAL tRP tRCD tRAS tRC
DQ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
66
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Full Page
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS BANK0 tCH NOPRE BANK0OR1 BANK0 COLUMN tCHI tCL
T1
T2
T3
T4
T5
T6
T259
T260
T261
T262
T263
T264
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH DIN0m-1 DIN 0m tDPL tRP
DQ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = full page Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
67
IS42S16100E, IS45S16100E
Write Cycle / Ping-Pong Operation (Bank Switching)
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 BANK1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1)
A0-A9 A10 A11 DQM
COLUMN AUTOPRE
ROW ROW
COLUMN AUTOPRE
ROW ROW
NOPRE BANK1
BANK0OR1 BANK0 BANK1 BANK0 tCH
tDS
tDH tDS DIN 0m
tDH tDS DIN 0m+1
tDH tDS DIN 0m+2
tDH tDS DIN 0m+3
(BANK0)
tDH tDS DIN 1m
tDH tDS DIN 1m+1
tDH tDS DIN 1m+2
tDH DIN 1m+3 tDPL tRCD
DQ
(BANK0TO1) (BANK0) (BANK0) (BANK0)
tRRD
tDPL
tRCD
(BANK1)
tRCD
tRAS tRC
(BANK0)
tRP
tRAS tRC
(BANK1) (BANK1)
tRAS tRC
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
68
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK1 BANK0 tCS tQMD BANK0 NOPRE NOPRE BANK1 BANK0 BANK0OR1 BANK1 BANK0
(1) (1)
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1
tCH tAC tAC tOH
DOUTo
tAC tLZ
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tAC tOH
DOUT n
tOH
DOUT n+1
tOH
DOUTo+1
DQ
tRCD tRAS tRC tCAC tCAC
tCAC tRQL tRP
tHZ
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
69
IS42S16100E, IS45S16100E
Read Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 BANK1 BANK0 tCS tQMD BANK1 BANK0 tCH tAC tLZ tAC tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm NOPRE
COLUMNn NOPRE
COLUMNo AUTOPRE NOPRE BANK1 BANK0 tQMD tAC tOH
DOUT m+1 DOUT n
BANK0AND1 BANK0OR1 BANK1 BANK0
tAC tOH
tAC tOH
DOUTo
tOH
DOUTo+1
DQ
tCAC
tCAC tRQL tRP
tHZ
tRCD tRAS tRC
tCAC
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
70
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Write Cycle / Page Mode
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS BANK0 BANK0 tCH NOPRE BANK1 NOPRE BANK1 NOPRE BANK1 BANK0 BANK0OR1 BANK1 BANK0
RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DINn
tDS
tDH tDS DINo
tDH DINo+1 tDPL tRP
DQ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
71
IS42S16100E, IS45S16100E
Write Cycle / Page Mode; Data Masking
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 BANK1 BANK0 NOPRE BANK1 BANK0 BANK1 BANK0 NOPRE NOPRE BANK1 BANK0 BANK1OR0
RAS
tCS
CAS
tCS
WE
tAS
(1) (1) (1)
A0-A9 A10 A11 DQM
COLUMNm
COLUMNn
COLUMNo AUTOPRE BANK0AND1
tCS
tCH
tDS
tDH tDS DIN m
tDH tDS DIN m+1
tDH DINn
tDS
tDH tDS DINo
tDH DINo+1 tDPL tRP
DQ
tRCD tRAS tRC
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
72
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
tCKS
tCKH
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS NOPRE BANK1 BANK0 BANK0OR1 BANK1 tQMD tCH tAC tAC tOH tOH
DOUT m+1 DOUT m
RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm AUTOPRE BANK0AND1
BANK0
DQ
tLZ tRCD tRAS tRC tCAC
tHZ tRP
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
73
IS42S16100E, IS45S16100E
Write Cycle / Clock Suspend
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 tCS NOPRE BANK1 BANK0 BANK0OR1 BANK1 BANK0 tCHI tCL tCKS tCKH
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK1 BANK0
tCH
tDS
tDH DIN m
tDS DIN m+1
tDH
DQ
tRCD tRAS tRC
tDPL tRP tRAS tRC
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
74
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tQMD tAC BANK0OR1 BANK0 tCH BANK0 ROW BANK1
RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm
ROW
tAC tOH
DOUT m
tAC tOH
DOUT m+1
tHZ tOH
DOUT m+2
DQ
tLZ tRCD tRAS tRC tCAC
tRQL tRP
tRCD tRAS tRP
Undefined
CAS latency = 3, burst length = 2 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
75
IS42S16100E, IS45S16100E
Write Cycle / Precharge Termination
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK0 tCS NOPRE BANK0 tCH BANK0OR1 BANK0 tCS tCH BANK0 ROW BANK1 tCHI tCL
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 DQM
COLUMNm
ROW
tDS
tDH tDS
DIN 0m DIN 0m+1
tDH tDS
DIN 0m+2
tDH
DQ
tRCD tRAS tRC
tRCD tRP tRAS tRP
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
76
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
IS42S16100E, IS45S16100E
Read Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 tCS tCS tQMD tQMD tAC tLZ tHZ tOH
DOUT m
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS RAS
tCS
CAS
tCS
WE
tAS
(1)
A0-A9 A10 A11 UDQM
COLUMNm AUTOPRE BANK0AND1
ROW ROW BANK0OR1 BANK1 tCH BANK0 BANK0 BANK1
tCH tAC tLZ
DOUT m+2
LDQM
tAC tHZ tOH
DOUT m+3
DQ8-15
tAC tLZ
tAC tOH
DOUT m
tHZ tOH
DOUT m+1
DQ0-7
tRCD tRAS tRC tCAC
tQMD
tRQL tRP
tRCD tRAS tRP
Undefined
CAS latency = 3, burst length = 4 Note1:A8,A9=Don'tCare.
Don'tCare
Integrated Silicon Solution, Inc. -- www.issi.com
Rev. D 08/24/09
77
IS42S16100E, IS45S16100E
Write Cycle / Byte Operation
T0 CLK
tCKS tCK tCKA tCH tCS
T1
tCHI
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
tCL
CKE
tCS
CS
tCH tCH tCH tAH ROW tAS tAH ROW tAS tAH BANK1 BANK0 NOPRE BANK1 BANK0 BANK0OR1 BANK1 tCH tCH tDS tDH DINm tDS tDH DINm tRCD tRAS tRC DIN m+1 tDS DIN m+3 tDPL tRP tRCD tRAS tRP tDH tDS DIN m+3 tDH BANK0 BANK0 |
